Home / PCB Design / PCB Design: The Complete Guide from Schematic to Fabrication

PCB Design: The Complete Guide from Schematic to Fabrication

PCB Design ✍ Oliver Adam ⏱ 24 min read August 22, 2026

## From Breadboard to Product

Breadboards tolerate mistakes; production PCBs do not. Learning the PCB workflow schematic → footprint → layout → DRC → Gerber → fab is what turns a working prototype into a manufacturable product. This hub links the complete PCB design path on Procirel. Including the trace-width maths that keeps boards from burning.

## What You Will Learn

– Schematic capture clean, reviewable schematics that others can read.
– Footprints matching symbols to real parts and checking pads before you route.
– Layout placement strategy, trace width for current, and return paths.
– Verification design rule checks and the errors that matter.
– Manufacturing exporting Gerbers and ordering from fab houses.
– Design math IPC-2221 trace sizing for current and temperature rise.

## The Learning Path

1. [How to Design a PCB](/tutorial/how-to-do-pcb-design) 10 min
Complete step-by-step guide from drawing your first schematic to ordering a real printed circuit board from JLCPCB for $2. Free software, real circuit case study, zero experience required.
2.
[Electronic Circuits Guide: From Basic C …
omponents to PCB Design](/tutorial/electronic-circuits) 18 min
An electronic circuit is simply a group of basic components such as resistors, capacitors, diodes, transistors, and IC. Connected together to control electricity and perform a task like lighting an LED. Sensing a signal, amplifying sound, or processing logic. For beginners the best approach is to start with very simple projects like LED, sensor. 555 timer circuits, practice first on a breadboard, and then move to PCBs. While learning how to read schematics, symbols, polarity, and series/parallel connections including the basic rule that when resistors are connected end-to-end (in series). The same current flows through each one and their values add up (Rtotal = R1 + R2 + R3), which increases total resistance and limits current flow. To keep circuits safe and reliable, focus on a few key rules. Use Ohm’s Law to choose correct resistor values, check power dissipation to avoid overheating. Add decoupling capacitors and proper grounding to reduce noise. By following these fundamentals and standard PCB practices, anyone can confidently understand schematics, build reliable circuits. Progress to real-world electronic projects.

> Live index: this list is generated from the site database when a new tutorial is published in this category, it appears here automatically.

## Design Rules of Thumb

## Frequently Asked Questions

KiCad, Altium or EasyEDA?
KiCad is free, open-source and fully professional our tutorials use it. Altium matters in large teams. EasyEDA is fine for quick 2-layer hobby boards integrated with fab houses.

What files do I send to the fab house?
The Gerber package (copper, silkscreen, mask, drill) plus a fab drawing if the board is complex. Never send your source project files.

How much does a small PCB run cost?
Prototype services commonly offer 5–10 boards of a 2-layer design for the price of shipping details are covered in the ordering tutorial.

## Engineering deep dive

The sections that follow are this pillar’s technical core: the reasoning, arithmetic and reference tables that every cluster guide below assumes, written to stand alone as well as to connect.

## The complete workflow, concept to courier

Professional PCB work is a pipeline: requirements, schematic capture, footprint verification, stackup planning, placement, routing, DRC, Gerber export, fab order, assembly, test. Skipping a stage does not save time, it relocates the cost to the most expensive place downstream. The pipeline entry points are [KiCad schematic capture](/tutorial/kicad-schematic-tutorial) and the [complete PCB guide](/tutorial/how-to-do-pcb-design).

The single habit that separates clean first revisions from three-spin projects: verify every footprint against the physical part with a 1:1 print, [footprint rules](/tutorial/pcb-footprint-design-rules).

## Placement is 80 percent of routing

Components placed with intent route themselves. The order that works: connectors and mechanical anchors first, then each IC surrounded by its decoupling and local passives, then power flow, then signals. The method with worked reasoning is [layout best practices](/tutorial/pcb-layout-best-practices), and the specific mistakes that generate re-spins are catalogued in [PCB design mistakes](/tutorial/pcb-design-mistakes) via the redirect from the old site.

Ground discipline follows placement: one unbroken plane under signals, because return current follows its trace, and a slot under a fast line is an antenna. The physics of return paths, stitching and the cost of split planes is the core of [ground planes and return paths](/tutorial/ground-planes-return-paths).

## Traces, vias and the arithmetic of copper

A trace is a resistor you draw. Current capacity follows IPC-2221 against temperature rise, automated in the [trace width calculator](/tools/pcb-trace-width) with the theory in [trace width guide](/tutorial/pcb-trace-width-guide). Vias add resistance and inductance, power transitions use arrays not single drills, and the families, through, blind, buried, are compared in [via types](/tutorial/pcb-via-types-guide).

| Feature | 2-layer hobby value | Fab limit |
|—|—|—|
| Min trace | 0.25 mm | 0.127 mm |
| Clearance | 0.25 mm | 0.127 mm |
| Via drill | 0.4 mm | 0.2 mm |

RF sections add impedance control: 50-ohm geometry, keep-outs under antennas and the whole layout lawbook in [RF PCB layout](/tutorial/rf-pcb-layout-guide).

## Power integrity and the decoupling system

Every IC switching at speed draws current in nanosecond bursts that no regulator can follow. The decoupling system, ceramic at the pin, bulk per cluster, reservoir at entry, supplies those bursts, and its effectiveness is geometry, not capacitance value. Placement physics and the failure modes it prevents fill [decoupling capacitor placement](/tutorial/decoupling-capacitor-placement).

Power distribution then has to arrive at all: rails sized with the trace calculator, planes stitched with via arrays, and regulation local to loads. The supply-side theory belongs to the power track, but the board-side delivery rules live here, and the two pillars meet at the regulator footprint.

## Design for manufacturing and assembly

Boards that work and boards that a factory can build are different achievements. DFM keeps traces above fab limits, announces controlled impedance, and respects solder-mask definition on fine pitch. DFA keeps assembly reworkable: thermal reliefs on plane pads, [assembly defects](/tutorial/pcb-assembly-defects) prevented rather than inspected, and panelisation thought through when volumes justify it.

Gerber handoff is the last quality gate: complete file set, preview in a viewer, and the fab’s own online check before paying, [Gerber files explained](/tutorial/gerber-files-explained). What happens after the courier leaves, etching, plating, mask, finish, is documented in [the manufacturing process](/tutorial/pcb-manufacturing-process) so design rules have a visible reason. VLSI perspective for the chip-scale curiosity: [what is VLSI](/tutorial/what-is-vlsi-design).

## Two worked board examples

**USB sensor node, 2 layers.** MCU, I2C sensor, USB connector. Placement: connector left, MCU centre with caps, sensor right. Routing: 0.25 mm signals, one 0.5 mm rail, ground plane unbroken, USB pair matched length. DRC clean at fab defaults, first-spin success follows the [workflow](/tutorial/pcb-layout-best-practices).

**Motor driver, 4 layers.** Power stage with 2 oz copper, 2 A rails sized by the [calculator](/tools/pcb-trace-width) at 10 C rise, gate loops short per the [MOSFET guide](/tutorial/mosfet-as-switch), thermal vias under the driver pad stitching to a dedicated plane. The layer-count decision, impedance, density and ground integrity, is argued in [the complete guide](/tutorial/how-to-do-pcb-design).

## Glossary of PCB terms

## High-speed is closer than you think

Edge rates, not clock rates, make a signal high-speed. A slow microcontroller with fast edges behaves like RF on every transition, and the boundary where ordinary traces become transmission lines arrives in ordinary hobby projects. The entry concepts, controlled impedance and return paths, are in [ground planes](/tutorial/ground-planes-return-paths), with the full RF treatment in [RF layout](/tutorial/rf-pcb-layout-guide).

The defensive rules cost nothing at design time: short loops, continuous planes, matched pairs and decoupling geometry, each already linked from this pillar’s clusters.

## Schematic quality that survives review

A schematic is a communication document. Functional blocks left to right, labelled nets instead of spaghetti, reference designators in sequence and power symbols used consistently, these habits make a review productive instead of archaeological. The conventions are taught with the tooling in [KiCad schematic capture](/tutorial/kicad-schematic-tutorial).

Reviews then catch what one mind misses: a colleague walking the return paths, checking the BOM against reality and questioning each footprint catches first-spin errors while they cost minutes instead of weeks. The [standards section](/tutorial/pcb-layout-best-practices) frames review as the cheapest test in the entire pipeline.

## From prototype to product run

The leap from one board to a product is procedural: design rule sets fixed to the fab, panelisation, test points, programming connectors and a documented bring-up procedure. The [DFM section](/tutorial/pcb-manufacturing-process) covers what factories grade, and the [assembly guide](/tutorial/pcb-assembly-defects) covers what assembly demands, from paste apertures to fiducials.

Cost engineering closes the gap: board size, layer count, finish and quantity each carry price tags with clean break-points. The pocket-friendly defaults, two layers, HASL, standard stackup, cover most products until volume argues otherwise, and knowing when it argues is part of the craft this track teaches.

## Library hygiene and project structure

A PCB project is only as reliable as its library: footprints verified once and reused, symbols with consistent pin ordering, and a project folder that carries its datasheets alongside its source. The KiCad workflow in [schematic capture](/tutorial/kicad-schematic-tutorial) builds this structure deliberately, and the footprint verification ritual in [footprint rules](/tutorial/pcb-footprint-design-rules) is the habit that keeps libraries trustworthy.

Version discipline completes hygiene: one project, one revision, one ZIP at every milestone. Gerbers from Tuesday’s schematic with Thursday’s layout have cost more prototype runs than any design error, and the free fix is process, not talent. The [Gerber guide](/tutorial/gerber-files-explained) closes the loop with the export checklist that makes each handoff auditable.

## Test, bring-up and the first power-on

Bring-up is a ceremony, not a moment: visual inspection, continuity of rails, current-limited first power, then rail voltages, then clocks, then signals, each step with the [bench supply](/tutorial/bench-power-supply-guide) standing guard at a current limit chosen to fail safely. Test points designed in from the start, per the [DFM sections](/tutorial/pcb-layout-best-practices), turn a blind debug into a guided one.

The methodical version takes twenty minutes; the improvised version takes a replacement board. Every experienced designer in this track’s expert sections tells the same story about the day they learned which of the two they were.

## The economics of iteration

Iteration is a budget line, and this track treats it as one. A two-layer hobby spin costs little; a four-layer impedance-controlled re-spin costs real money and two weeks. The lever that moves both is front-loaded verification: footprints at 1:1, DRC continuous, Gerber preview always, because every error caught before the order is free and every error after it is a re-spin.

The mature position on iteration is neither fear nor indulgence: plan for one revision in any new design, budget it, and spend it learning rather than rushing. Designers who ship revision three as revision one did their revision zero on paper, with the checklist this track provides.

## The topical map

14 guides hang from this pillar. Each entry below is written in this page’s own voice, a one-line summary of what that guide adds to the track, because the guide’s own abstract is one click away:
1. **[How to Design a PCB | PCB Design Guide](/tutorial/how-to-do-pcb-design)** — Complete step-by-step guide from drawing your first schematic to ordering a real printed circuit board from JLCPCB for $2; the hands-on half of this pillar’s complete step-by-step story.
2. **[Electronic Circuits Guide: From Basic Components to PCB Design](/tutorial/electronic-circuits)** — An electronic circuit is simply a group of basic components such as resistors; the hands-on half of this pillar’s an electronic story.
3. **[Common PCB Assembly Defects and How to Prevent Them](/tutorial/pcb-assembly-defects)** — Tombstones; the hands-on half of this pillar’s tombstones story.
4. **[How PCBs Are Made: From Copper Clad to Your Door](/tutorial/pcb-manufacturing-process)** — Etching; the hands-on half of this pillar’s etching story.
5. **[Gerber Files: What Each Layer File Means](/tutorial/gerber-files-explained)** — Copper; the hands-on half of this pillar’s copper story.
6. **[Decoupling Capacitor Placement: The Physics of “Put It Closer”](/tutorial/decoupling-capacitor-placement)** — Why 100 nF goes at the pin; the hands-on half of this pillar’s why 100 story.
7. **[PCB Vias: Through, Blind and Buried Types and Trade-offs](/tutorial/pcb-via-types-guide)** — What each via type costs and earns; the hands-on half of this pillar’s what each story.
8. **[PCB Trace Width: Sizing Copper for Current and Heat](/tutorial/pcb-trace-width-guide)** — IPC-2221 maths; the hands-on half of this pillar’s ipc-2221 maths story.
9. **[Ground Planes and Return Paths: Signal Integrity Foundations](/tutorial/ground-planes-return-paths)** — Current always loops how reference planes shape return paths; the hands-on half of this pillar’s current always story.
10. **[PCB Layout Best Practices: Placement to Routing](/tutorial/pcb-layout-best-practices)** — Component placement strategy; the hands-on half of this pillar’s component placement story.
11. **[PCB Footprints: Pads, Courtyards and the Checks That Matter](/tutorial/pcb-footprint-design-rules)** — Pad geometry; the hands-on half of this pillar’s pad geometry story.
12. **[KiCad Schematic Capture: Clean Beginnings](/tutorial/kicad-schematic-tutorial)** — Symbols; the hands-on half of this pillar’s symbols story.
13. **[RF PCB Layout: Rules for WiFi, LoRa and Beyond](/tutorial/rf-pcb-layout-guide)** — Transmission lines; the hands-on half of this pillar’s transmission lines story.
14. **[What Is VLSI Design? Building Chips With Billions of Transistors](/tutorial/what-is-vlsi-design)** — From RTL to silicon the design flow; the hands-on half of this pillar’s from rtl story.

## A four-week study plan for this track

The same map as a calendar, one guide per session, roughly an hour each plus bench time. Adapt the pace freely, the order is what matters:
– Week 1, session 1: Read and build [how to design a pcb | pcb design guide](/tutorial/how-to-do-pcb-design).
– Week 1, session 2: Work through [electronic circuits guide: from basic components to pcb design](/tutorial/electronic-circuits).
– Week 1, session 3: Bench-test [common pcb assembly defects and how to prevent them](/tutorial/pcb-assembly-defects).
– Week 1, session 4: Study and wire [how pcbs are made: from copper clad to your door](/tutorial/pcb-manufacturing-process).
– Week 2, session 1: Apply [gerber files: what each layer file means](/tutorial/gerber-files-explained).
– Week 2, session 2: Measure along with [decoupling capacitor placement: the physics of “put it closer”](/tutorial/decoupling-capacitor-placement).
– Week 2, session 3: Practice [pcb vias: through, blind and buried types and trade-offs](/tutorial/pcb-via-types-guide).
– Week 2, session 4: Revisit and extend [pcb trace width: sizing copper for current and heat](/tutorial/pcb-trace-width-guide).
– Week 3, session 1: Read and build [ground planes and return paths: signal integrity foundations](/tutorial/ground-planes-return-paths).
– Week 3, session 2: Work through [pcb layout best practices: placement to routing](/tutorial/pcb-layout-best-practices).
– Week 3, session 3: Bench-test [pcb footprints: pads, courtyards and the checks that matter](/tutorial/pcb-footprint-design-rules).
– Week 3, session 4: Study and wire [kicad schematic capture: clean beginnings](/tutorial/kicad-schematic-tutorial).
– Week 4, session 1: Apply [rf pcb layout: rules for wifi, lora and beyond](/tutorial/rf-pcb-layout-guide).
– Week 4, session 2: Measure along with [what is vlsi design? building chips with billions of transistors](/tutorial/what-is-vlsi-design).

## What you will be able to do after this track

– Choose and apply the track’s core methods to a fresh problem, not just the worked examples.
– Predict results before measuring, and diagnose honest disagreements between the two.
– Use the track’s linked calculators fluently, with the formulas and standards behind them.
– Read a datasheet, a schematic and a specification with the same confidence as prose.
– Build the track’s capstone projects and document them to the editorial standard this site holds itself to.

## Track questions, answered plainly

**Two layers or four for my first board?**
Two. Every skill in this track is teachable on two layers, and four becomes the answer when ground integrity, density or controlled impedance demand it, which you will recognise by then.

**How cheap are prototype runs really?**
Five boards of a small 2-layer design commonly cost less than shipping from the major fabs. The Gerber guide walks the exact order checklist.

**Why did my footprint fail even though DRC passed?**
DRC checks rules, not reality. Only a 1:1 print against the physical part verifies pads, which is why the footprint ritual exists before layout.

**Do I need to learn KiCad or is EasyEDA fine?**
KiCad, for this track, because its transparent toolchain and library control suit the documentation habits taught here. EasyEDA remains legitimate for quick boards.

**What single habit prevents the most re-spins?**
Verifying footprints against datasheets before routing. It catches the errors DRC cannot imagine.

**How long from schematic to boards in hand?**
A first 2-layer board is an evening of schematic, a weekend of layout, then fab transit days. The workflow guide sequences it honestly.

## Related tracks and where they meet this one

Topical authority crosses category borders, and engineers cross them daily. These adjacent pillars share concepts, components and instruments with this track:
– [Electronics Fundamentals: The Complete Guide (Components, Theory…](/tutorial/electronics-fundamentals-complete-guide) — the electronics fundamentals pillar. The cornerstone guide to electronics theory every component, law and circuit concept on one page, linking to every fundamentals tutorial on the site.
– [Arduino: The Complete Guide From First Blink to Working Robots](/tutorial/arduino-complete-guide) — the arduino projects pillar. The structured Arduino path: setup, sensors, displays, motors and complete builds every Arduino tutorial on the site, in the order you should learn them.
– [IoT & ESP32: The Complete Smart Devices Guide](/tutorial/iot-esp32-complete-guide) — the iot sensors pillar. Everything WiFi, MQTT and sensors: build connected devices that never brown out the complete IoT path with ESP32, MQTT and smart-home builds.
– [Electrical Engineering: The Complete Practical Guide (Power, Moto…](/tutorial/electrical-engineering-complete-guide) — the electrical engineering pillar. Power systems, transformers, motors and safe wiring the complete electrical path from single-phase circuits to industrial machines.

## The calculators behind this track

Every formula on this page and in the clusters runs instantly in the toolbox, no signup, client-side:
– [Ohm’s Law Calculator](/tools/ohms-law) — Ohm’s Law defines the fundamental relationship between voltage (V), current (I), and resistance (R) in any electrical ci
– [Resistor Color Code](/tools/resistor-color-code) — Through-hole resistors use colored bands painted on the body to indicate their resistance value
– [LED Resistor Calculator](/tools/led-resistor) — Every LED needs a current-limiting resistor to prevent it from drawing too much current and burning out
– [Voltage Divider Calculator](/tools/voltage-divider) — A voltage divider uses two series resistors to produce an output voltage that is a fraction of the input voltage
– [555 Timer Astable Mode](/tools/timer-555-astable) — In astable mode, the NE555 timer generates a continuous square wave output without any external trigger
– [555 Timer Monostable Mode](/tools/timer-555-monostable) — In monostable (one-shot) mode, the 555 timer outputs a single HIGH pulse of a precisely defined duration when triggered
– [RC Time Constant](/tools/rc-time-constant) — The RC time constant (τ = tau) defines how fast a capacitor charges or discharges through a resistor
– [Capacitor Code (3-Digit)](/tools/capacitor-code) — Ceramic and film capacitors often have a 3-digit code printed on them instead of the full value

## Questions about this track

**How long does the full track take?**
Sum the read times in the map and expect roughly double with bench practice alongside. The guides are written to be built, not skimmed.

**Can I skip guides inside the track?**
The map is ordered but each entry names what it assumes. Skip freely when a guide’s opening sentences tell you things you already own.

**Which calculator should I bookmark first?**
The one matching your current cluster, but the full toolbox is one click from every page header.

**Is this track maintained?**
Guides carry review dates, and corrections are public through the [editorial process](/editorial-team).

—

**How to use this pillar.** Read the deep dive top to bottom for a complete foundation, then enter any cluster from the topical map. Every guide assumes this page’s vocabulary, every calculator verifies its arithmetic, and the [author’s profile](/author/oliver-adam) stands behind both.

Written by Oliver Adam

M.S. Electronics (Power Systems), Founder & Lead Author. Every guide is physically built and measured on the bench before publication. See the editorial standards on the editorial team page.