ProcirelPCB Footprints: Pads, Courtyards and the Checks That Matter
A footprint is where the logical part meets physical reality. Get the copper wrong by half a millimetre and the finest circuit works loose. Most footprint errors are boring, measurable and entirely preventable.
> At a glance: 7 minute guide · part 2 of 10 in the PCB design complete guide track · includes a worked example and a quick-reference table.
## Pad geometry from the datasheet
Land patterns come from the package drawing: pad width × length and pitch. For SMD parts, follow the IPC-computed pattern in the manufacturer’s datasheet. For THT, hole = lead diameter + 0. 2 mm, annular ring ≥ 0. 15 mm.
| Feature | Rule of thumb | Why |
| — | — | — |
| THT hole | Lead + 0.2 mm | Insertion + solder flow |
| Annular ring | ≥ 0.15 mm | Drill breakout margin |
| SMD pad | Datasheet pattern | Self-centring in reflow |
| Courtyard | Body + clearance | Assembly collisions |
| Pin-1 mark | Silk dot + bevel | Orientation both ways |
## Courtyards and courtyard exceptions
What this means at the bench. Each footprint carries a courtyard the keep-out rectangle including part body and hand-soldering space. Courtyard overlaps flag at DRC. Deliberate exceptions (dense connectors) get documented, never silently accepted.
## Verify against the physical part
Print footprints at 1:1 and seat real components before layout. Check polarity marks, pin-1 indicators and thermal pad openings. Ten minutes with paper and calipers prevents a fab cycle of discovery.
## How to apply this in your build
Work through the sequence below each step assumes the previous one passed. For numbers that need calculating, the linked tools at the end of this guide do the arithmetic instantly.
1. Pull the package drawing from the datasheet
2. Build or verify pads to the recommended pattern
3. Print 1:1 and seat real components
4. Check pin-1 and polarity markings on silk
### Worked example
An SOT-23 footprint copied from a mismatched library soldered two boards badly the pitch was 0. 95 mm instead of 1. 00 mm. A caliper check against the drawing caught it before the third. Run the numbers yourself with the PCB Trace Width and the result should agree to within rounding.
> Practical note from the bench. Footprint checklists live inside our project folders: package drawing screenshot, measured pads, 1:1 print verified three lines per part.
## Field mistakes we see again and again
– Mixing metric and imperial library parts in one design
– Silkscreen over pads legibility dies and soldering suffers
– Thermal pads with no via array heat and RF grounding both suffer
## Key takeaways
– Pad geometry from the datasheet the foundation of this guide; revisit it if any measurement here surprises you.
– Courtyards and courtyard exceptions the foundation of this guide; revisit it if any measurement here surprises you.
– Verify against the physical part the foundation of this guide; revisit it if any measurement here surprises you.
## Prerequisites and preparation
Before starting. Pull the package drawing from the datasheet and build or verify pads to the recommended pattern. Keep the [PCB Trace Width](/tools/pcb-trace-width) open every number in the worked example is reproducible. Total time including the bench steps: about 6–7 minutes.
## Who benefits most
Hobbyists meeting this topic for the first time, students who want the version with real numbers instead of abstract symbols. Returning engineers refreshing a corner of the craft. The mistake list alone justifies the visit every entry in it was learned the expensive way.
### Quick reference card
| Aspect | Where to find it in this guide |
| — | — |
| Core theory | Pad geometry from the datasheet |
| Application steps | How to apply this in your build |
| Worked numbers | Worked example |
| Failure modes | Field mistakes we see again and again |
## How this fits the PCB design complete guide track
This guide is one stop in the structured learning path. Start from the [PCB design complete guide](/tutorial/pcb-design-complete-guide) pillar page for the full map, or continue with [layout best practices](/tutorial/pcb-layout-best-practices) and [assembly defects guide](/tutorial/pcb-assembly-defects). For the arithmetic, open the [PCB Trace Width](/tools/pcb-trace-width).
## Frequently asked questions
Can I reuse the library footprint for a “similar” part?
Only after checking the drawing package names lie across vendors.
What is a courtyard exemption?
A documented DRC exception where parts intentionally sit closer; record why in the design notes.
Is there a calculator for this?
Yes the [PCB Trace Width](/tools/pcb-trace-width) tool runs the formulas from this guide instantly, client-side, with no signup.
## Where to go next
– The complete pcb design guide: [PCB Design complete guide](/tutorial/pcb-design-complete-guide)
– Read next: [rf pcb layout: rules for wifi, lora and beyond](/tutorial/rf-pcb-layout-guide)
– Also in this track: [what is vlsi design?
– Continue with: [kicad schematic capture: clean beginnings](/tutorial/kicad-schematic-tutorial)
– Calculate as you go: [PCB trace width calculator](/tools/pcb-trace-width) · [resistor value decoder](/tools/resistor-color-code) · [SMD code decoder](/tools/smd-resistor-code)
– Bookmark this page against the day a measurement surprises you. Most readers return to the table and the mistake list first, and that is the correct order.
## Bench verification habits
When a result here disagrees with your expectation, write down both numbers before changing anything. The gap between predicted and measured is where the real engineering lives. It is usually a tolerance, a parasitic or an assumption that was never checked.
Keep a lab notebook entry for every build in this track. The measured values, the deviations from the guide and the reason for each. Six months from now, those notes are worth more than any tutorial. They describe your bench and your components rather than a general case.
## Formulas and checks from this guide
Verification checklist for this track: run DRC early and often, verify footprints against the datasheet drawing. Walk the return path of every fast signal before ordering. A five-minute Gerber preview has saved more fab cycles than any other habit.
Bookmark this page against your next build in the track. The checklist above is the same one used across 15 guides in this series.
## From our lab notebook
Run DRC continuously, then once more after every final edit. The last small change breaks the most boards.
Two for hobby density, four the moment ground integrity or impedance matters. The cost gap has collapsed.
## Final note from the author
A note on layout order, which decides most boards in this track: connectors, then ICs with decoupling, then critical routes, then fill. Reversing that order is how revisions multiply.
Working through Pad geometry from the datasheetand Courtyards and courtyard exceptions with that habit in mind takes minutes, and it is the difference between reading about this topic and owning it.